clock jitter
基本解释
- 时钟抖动
英汉例句
- The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。 - Based on Gaussian random process model and continuous-time system in time domain , this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
jeit.ie.ac.cn - The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
双语例句
词组短语
- Absolute Clock Period Jitter 振动周期
- Clock Input Jitter 时钟输入抖动
- Low clock jitter 低时钟抖动
- accumulated clock jitter 累积时钟抖动
- Sample Clock Jitter 采样时钟抖动
短语
专业释义
- 时钟抖动
This paper studies the ADC measuring clock jitter technology based on simple interference sampling.
本文基于简单相干采样法研究了ADC测量时钟抖动的技术。 - 低抖动
Because ring oscillator achieves high stability and low clock jitter output signal, it is always selected.
而环形振荡器由于其能够获得稳定度高、低抖动时钟输出信号,且易于片上集成,从而成为时钟发生器的首选。计算机科学技术
- 时钟抖动