clock data recovery

基本解释

The main circuits include a trans-impedance amplifier (TIA), a limiting amplifier, a clock and data recovery (CDR) unit, and a (1∶4) demultiplexer (DEMUX).
主要电路包括前置放大、限幅放大、时钟恢复、数据判决和1∶4分接。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。