pipelined analog-to-digital converter

基本解释

A 13bit, pipelined analog-to-digital converter(ADC)designed to achieve high linearity is described.
介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described .
设计了一个用于流水线型模数转换器的低压采样保持电路。
To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter(ADC), a new statistics-based background calibration technique is presented.
为了降低流水线模数转换器中数字校准电路的规模和功耗，提出了一种新的基于信号统计规律的后台数字校准技术。