signal dispose

基本解释

The schemes to dispose of reset signal and clock signal in VHDL high-level synthesis are given also.
還給出了高級綜郃中複位信號和時鍾信號的処理方法。
The hardware of the system is composed of three parts: dispose the analog signal to be in the right range;
撥道系統的硬件部分爲三個部分：對輸入的模擬信號進行処理使信號的範圍達到要求；
At first the filter based on mathematical morphology is applied to dispose the disturbance signal in advance. A multiple structuring element complex filter is created to restrain many kinds of noise.
首先利用數學形態學對擾動波形進行預処理，再使用分形技術檢測電能質量擾動，最後用模式識別確定擾動類型。

信號処理
Hardware system use TI company's DSP chip TMS320LF2407A for core. Because of DSP chip have quickly signal dispose speed,so insure system high detect precision.
其中硬件系統以TI公司的DSP芯片TMS320LF2407A爲核心,由於DSP芯片的信號処理速度快,確保了本系統的高測量精度。